function startTau_generic_Generated.m(oFRDReg, options)
    arguments
        oFRDReg
        options.sTimeOut (1,1) double = 10.0
    end

    % Generated from sequence: LBDB11_Start_Tau_generic_Copy
    % Sequence ID: 1722837829


    % ------ reset DUT and put into IDLE ------
    % Unsupported command type: DisplayController_Command_SetResetNPinState
    % Unsupported command type: DisplayController_Command_SetClkMirror
    % valid for 10MHz input-clock
    oFRDReg.CLK_PLL.CLK_PLL = 3857; % 0x0F11

    % Wait for driver entering IDLE...
    sTimeOut = options.sTimeOut;
    sStart = tic;
    while(oFRDReg.OP_STATUS.opmode ~= 1)
        if toc(sStart) > sTimeOut
            error('ifx:runtime_error', 'Timeout waiting for OP_STATUS.opmode to equal 1');
        end
    end

    % ------ MSI config ------
    oFRDReg.MSI.vcm_sel = 2;
    oFRDReg.MSI.cmp_clk_provision = 1;
    oFRDReg.MSI.ib_sel = 4;
    oFRDReg.MSI.ib_source_sel = 1;

    % ------ Slow/Fast MSI config ------
    oFRDReg.CH1_MSI1.peak_det_source = 0;
    oFRDReg.CH1_MSI1.peak_det_pol = 0;
    oFRDReg.CH1_MSI1.tia_res_sel = 15;
    oFRDReg.CH1_MSI1.tia_cap_sel = 15;
    oFRDReg.CH1_MSI1.sah_tc = 2;
    oFRDReg.CH1_MSI1.swap_polarity = 0;
    oFRDReg.CH1_MSI2.sah_refdac_sel = 1;
    oFRDReg.CH1_MSI2.sah_en = 0;
    oFRDReg.CH1_MSI2.refdac_en = 1;
    oFRDReg.CH1_MSI2.refdac_sel = 4;
    oFRDReg.CH1_MSI2.ref_div_trim = 5;
    oFRDReg.CH0_MSI1.peak_det_source = 0;
    oFRDReg.CH0_MSI1.peak_det_pol = 0;
    oFRDReg.CH0_MSI1.tia_res_sel = 15;
    oFRDReg.CH0_MSI1.tia_cap_sel = 15;
    oFRDReg.CH0_MSI1.sah_tc = 2;
    oFRDReg.CH0_MSI1.swap_polarity = 0;
    oFRDReg.CH0_MSI2.sah_refdac_sel = 1;
    oFRDReg.CH0_MSI2.sah_en = 0;
    oFRDReg.CH0_MSI2.refdac_en = 1;
    oFRDReg.CH0_MSI2.refdac_sel = 0;
    oFRDReg.CH0_MSI2.ref_div_trim = 0;

    % ------ Slow/Fast subtiming config ------
    oFRDReg.CH1_ST_MODULO.cnt_value = 7000;
    oFRDReg.CH1_ST_POS.cnt_value = 0;
    oFRDReg.CH1_ST_MOV.cnt_value = 3500;
    oFRDReg.CH1_ST_DRIVE_ON.cnt_value = 3500;
    oFRDReg.CH1_ST_DRIVE_OFF_MIN.cnt_value = 262;
    oFRDReg.CH1_ST_DRIVE_OFF.cnt_value = 263;
    oFRDReg.CH1_ST_DRIVE_OFF_MAX.cnt_value = 2188;
    oFRDReg.CH0_ST_MODULO.cnt_value = 1700;
    oFRDReg.CH0_ST_POS.cnt_value = 0;
    oFRDReg.CH0_ST_MOV.cnt_value = 850;
    oFRDReg.CH0_ST_DRIVE_ON.cnt_value = 850;
    oFRDReg.CH0_ST_DRIVE_OFF_MIN.cnt_value = 54;
    oFRDReg.CH0_ST_DRIVE_OFF.cnt_value = 55;
    oFRDReg.CH0_ST_DRIVE_OFF_MAX.cnt_value = 805;

    % ------ Slow/Fast ADC config ------
    oFRDReg.CH1_ST_ADC_VTEMP.cnt_value = 1;
    oFRDReg.CH1_ST_ADC_MIRRCURR.cnt_value = 88;
    % currently disabled by setting to MODULO+1
    oFRDReg.CH1_ST_ADC_HVD.cnt_value = 7001;
    oFRDReg.CH1_ADC_SCHED1.angle_amplitude = 2;
    oFRDReg.CH1_ADC_SCHED2.hv = 200;
    oFRDReg.CH1_ADC_SCHED3.temperature = 100;
    oFRDReg.CH0_ST_ADC_VTEMP.cnt_value = 1;
    oFRDReg.CH0_ST_ADC_MIRRCURR.cnt_value = 45;
    % currently disabled by setting to MODULO+1
    oFRDReg.CH0_ST_ADC_HVD.cnt_value = 1701;
    oFRDReg.CH0_ADC_SCHED1.angle_amplitude = 2;
    oFRDReg.CH0_ADC_SCHED2.hv = 200;
    oFRDReg.CH0_ADC_SCHED3.temperature = 100;

    % ------ Slow/Fast Amp.-Sense + control config ------

    % slow - amplitude detection
    oFRDReg.CH1_AMPL_SENSE1.method = 0;
    oFRDReg.CH1_AMPL_SENSE1.diff_comp_pol = 0;
    oFRDReg.CH1_AMPL_SENSE1.asym_comp_en = 1;
    oFRDReg.CH1_AMPL_SENSE1.alpha_filter = 5;
    oFRDReg.CH1_AMPL_SENSE1.filter_en = 1;
    oFRDReg.CH1_MSI2.sah_refdac_sel = 1;
    oFRDReg.CH1_MSI2.sah_en = 0;
    oFRDReg.CH1_MSI2.refdac_en = 1;
    oFRDReg.CH1_MSI2.refdac_sel = 0;
    oFRDReg.CH1_MSI2.ref_div_trim = 0;
    oFRDReg.CH1_ST_AMPL_DET_START.cnt_value = 6193;
    oFRDReg.CH1_ST_AMPL_DET_STOP.cnt_value = 6543;
    oFRDReg.CH1_ST_AMPL_CTRL_SETPOINT.cnt_value = 6368;
    oFRDReg.CH1_ST_CMP_DIFF_EN_START.cnt_value = 3500;
    oFRDReg.CH1_ST_CMP_DIFF_EN_STOP.cnt_value = 175;

    % slow - amplitude control
    oFRDReg.CH1_AMPL_CTRL1.means_of_control = 0;
    oFRDReg.CH1_AMPL_CTRL1.i_gain = 2;
    oFRDReg.CH1_AMPL_CTRL2.p_gain = 20;
    oFRDReg.CH1_AMPL_CTRL1.source_pid = 1;
    oFRDReg.CH1_ST_CONTROL_ACTION.cnt_value = 262;
    oFRDReg.CH1_ST_CONTROL_ACTION.en = 1;
    oFRDReg.CH1_AMPL_CTRL1.phase_comp_en = 1;
    oFRDReg.CH1_AMPL_CTRL1.phase_comp_op = 1;

    % slow - enable amplitude sensing
    oFRDReg.CH1_CFG.ampl_sense_en = 1;

    % fast - peak sensing

    % for anti phase drive the tracking period needs to be very narrow otherwise inhibiting happens
    oFRDReg.CH0_ST_MIRRCURR_PEAK_START.cnt_value = 1029;
    oFRDReg.CH0_ST_MIRRCURR_PEAK_STOP.cnt_value = 54;
    oFRDReg.CH0_ST_MIRRCURR_PEAK_RESET.cnt_value = 828;
    oFRDReg.CH0_ST_MIRRCURR_PEAK_URESET.cnt_value = 939;

    % fast - amplitude detection
    oFRDReg.CH0_AMPL_SENSE1.method = 0;
    oFRDReg.CH0_AMPL_SENSE1.diff_comp_pol = 0;
    oFRDReg.CH0_AMPL_SENSE1.asym_comp_en = 1;
    oFRDReg.CH0_AMPL_SENSE1.alpha_filter = 7;
    oFRDReg.CH0_AMPL_SENSE1.filter_en = 0;
    oFRDReg.CH0_MSI2.sah_refdac_sel = 1;
    oFRDReg.CH0_MSI2.sah_en = 0;
    oFRDReg.CH0_MSI2.refdac_en = 1;
    oFRDReg.CH0_MSI2.refdac_sel = 0;
    oFRDReg.CH0_MSI2.ref_div_trim = 0;
    oFRDReg.CH0_ST_AMPL_DET_START.cnt_value = 1188;
    oFRDReg.CH0_ST_AMPL_DET_STOP.cnt_value = 1366;
    oFRDReg.CH0_ST_AMPL_CTRL_SETPOINT.cnt_value = 1277;
    oFRDReg.CH0_ST_CMP_DIFF_EN_START.cnt_value = 850;
    oFRDReg.CH0_ST_CMP_DIFF_EN_STOP.cnt_value = 89;
    oFRDReg.CH0_ST_AMPL_SH_START.cnt_value = 1342;
    oFRDReg.CH0_ST_AMPL_SH_STOP.cnt_value = 1432;

    % fast - amplitude control
    oFRDReg.CH0_AMPL_CTRL1.means_of_control = 0;
    oFRDReg.CH0_AMPL_CTRL1.i_gain = 100;
    oFRDReg.CH0_AMPL_CTRL2.p_gain = 100;
    oFRDReg.CH0_AMPL_CTRL1.source_pid = 1;
    oFRDReg.CH0_ST_CONTROL_ACTION.cnt_value = 54;
    oFRDReg.CH0_ST_CONTROL_ACTION.en = 1;
    oFRDReg.CH0_AMPL_CTRL1.phase_comp_en = 1;
    oFRDReg.CH0_AMPL_CTRL1.phase_comp_op = 1;

    % fast - enable amplitude sensing
    oFRDReg.CH0_CFG.ampl_sense_en = 1;

    % ------ Slow/Fast Phase-control config ------

    % slow
    oFRDReg.CH1_ST_PHASEDET_START.cnt_value = 6825;
    oFRDReg.CH1_ST_PHASEDET_STOP.cnt_value = 175;
    oFRDReg.CH1_ST_ZCREF_RESET.cnt_value = 3500;
    oFRDReg.CH1_ST_CMP_SUM_EN_START.cnt_value = 6781;
    oFRDReg.CH1_ST_CMP_SUM_EN_STOP.cnt_value = 175;
    oFRDReg.CH1_ST_CONTROL_ACTION.cnt_value = 176;
    oFRDReg.CH1_ST_CONTROL_ACTION.en = 1;
    oFRDReg.CH1_PHASE_CTRL1.i_gain = 255;
    oFRDReg.CH1_PHASE_CTRL2.p_gain = 600;
    oFRDReg.CH1_PHASE_CTRL1.asym_comp_en = 1;
    oFRDReg.CH1_PHASE_CTRL1.means_of_control = 0;
    oFRDReg.CH1_PHASE_CTRL3.delay = 3;

    % fast
    oFRDReg.CH0_ST_PHASEDET_START.cnt_value = 1655;
    oFRDReg.CH0_ST_PHASEDET_STOP.cnt_value = 45;
    oFRDReg.CH0_ST_ZCREF_RESET.cnt_value = 850;
    oFRDReg.CH0_ST_CMP_SUM_EN_START.cnt_value = 1610;
    oFRDReg.CH0_ST_CMP_SUM_EN_STOP.cnt_value = 45;
    oFRDReg.CH0_ST_CONTROL_ACTION.cnt_value = 49;
    oFRDReg.CH0_ST_CONTROL_ACTION.en = 1;
    oFRDReg.CH0_PHASE_CTRL1.i_gain = 255;
    oFRDReg.CH0_PHASE_CTRL2.p_gain = 600;
    oFRDReg.CH0_PHASE_CTRL1.asym_comp_en = 1;
    oFRDReg.CH0_PHASE_CTRL1.means_of_control = 0;
    oFRDReg.CH0_PHASE_CTRL3.delay = 1;

    % ------ Slow/Fast HV config ------
    % approximately HV= 0,72 * lead -> 72V
    oFRDReg.CH1_HVD1.lead = 100;
    oFRDReg.CH1_HVD3.lag = 100;
    oFRDReg.CH1_HVD2.disch_trim = 7;
    oFRDReg.CH1_HVD1.en = 1;
    oFRDReg.CH1_HVD1.peak_det_res_zcs = 10;
    oFRDReg.CH1_HVD2.pol = 1;
    oFRDReg.CH1_HVD2.en_vmax_hv_adc = 1;
    oFRDReg.CH1_ST_HVD_PEAK_START.cnt_value = 0;
    oFRDReg.CH1_ST_HVD_PEAK_STOP.cnt_value = 1750;
    oFRDReg.CH1_ST_HVD_PEAK_RESET.cnt_value = 3500;
    oFRDReg.CH1_ST_HVD_PEAK_URESET.cnt_value = 7000;
    % approximately HV= 0,72 * lead -> 72V
    oFRDReg.CH0_HVD1.lead = 100;
    oFRDReg.CH0_HVD3.lag = 100;
    oFRDReg.CH0_HVD2.disch_trim = 7;
    oFRDReg.CH0_HVD1.en = 1;
    oFRDReg.CH0_HVD1.peak_det_res_zcs = 10;
    oFRDReg.CH0_HVD2.pol = 1;
    oFRDReg.CH0_HVD2.en_vmax_hv_adc = 1;
    oFRDReg.CH0_ST_HVD_PEAK_START.cnt_value = 0;
    oFRDReg.CH0_ST_HVD_PEAK_STOP.cnt_value = 716;
    oFRDReg.CH0_ST_HVD_PEAK_RESET.cnt_value = 850;
    oFRDReg.CH0_ST_HVD_PEAK_URESET.cnt_value = 1611;

    % ------ Fref Master-Slave config ------

    % Ratio: a=718, b=179, a/b=4.0112, k=2, LJRate=39.2, Tau_generic on B11
    oFRDReg.FREF_MOD1_INT.mod1_int_part = 13645;
    oFRDReg.FREF_MOD1_FRACT1.mod1_fract_part_msb = 732;
    oFRDReg.FREF_MOD1_FRACT2.mod1_fract_part_lsb = 125;
    oFRDReg.CH1_CFG.pos_source = 1;
    oFRDReg.FREF1.fref1 = 1;
    oFRDReg.FREF1.mode_axis0 = 3;
    oFRDReg.FREF1.mode_axis1 = 0;
    oFRDReg.FREF1.period_axis = 1;
    oFRDReg.FREF1.periodic_sd_output_en = 1;
    oFRDReg.FREF1.synch_at_lj_fs_en = 1;
    oFRDReg.FREF_SMART_START.threshold = 10;
    oFRDReg.FREF_SMART_START.en = 0;
    oFRDReg.CH1_FREQ_CTRL1.means_of_control = 1;
    oFRDReg.CH1_FREQ_CTRL1.phase_comp_en = 0;
    oFRDReg.FREF_WINDOW.window_width = 20;
    oFRDReg.LJ_LOCK1.liss_f_s_duration = 15;
    oFRDReg.FREF_DELAY_CH1.delay = 0;
    oFRDReg.FREF1.delay_axis1_en = 0;
    oFRDReg.FREF_LJ_PERIOD1.lj_period_lsb = 178;
    oFRDReg.FREF1.en = 1;

    % ------ Slow Freq.-control config ------
    oFRDReg.CH1_FREQ_CTRL1.i_gain = 40;
    oFRDReg.CH1_FREQ_CTRL2.p_gain = 30;
    oFRDReg.CH1_FREQ_CTRL3.d_gain = 0;
    oFRDReg.CH1_FREQ_CTRL1.source_pid = 1;
    oFRDReg.CH1_FREQ_CTRL3.alpha_f = 5;
    oFRDReg.CH1_FREQ_CTRL5.d_limit_f = 3000;
    oFRDReg.CH1_FREQ_CTRL6.f_limit_top = 2;
    oFRDReg.CH1_FREQ_CTRL7.f_limit_bottom = 0;

    % ------ Inhibiting config ------
    oFRDReg.HVD_INHIBIT1.inhibit_ctrl_en = 1;
    oFRDReg.HVD_INHIBIT2.inhibit_time_switch_hv_off = 123;
    oFRDReg.HVD_INHIBIT2.inhibit_time_switch_hv_on = 123;
    oFRDReg.CH1_ST_INHIBIT1_HV_CH0_START.cnt_value = 6589;
    oFRDReg.CH1_ST_INHIBIT1_HV_CH0_STOP.cnt_value = 175;
    oFRDReg.CH1_ST_INHIBIT2_HV_CH0_START.cnt_value = 5957;
    oFRDReg.CH1_ST_INHIBIT2_HV_CH0_STOP.cnt_value = 6543;
    oFRDReg.CH0_ST_INHIBIT1_HV_CH1_START.cnt_value = 1546;
    oFRDReg.CH0_ST_INHIBIT1_HV_CH1_STOP.cnt_value = 45;
    oFRDReg.CH0_ST_INHIBIT2_HV_CH1_START.cnt_value = 1079;
    oFRDReg.CH0_ST_INHIBIT2_HV_CH1_STOP.cnt_value = 1366;
    % Go into operation mode
    oFRDReg.OP_CFG.op_en = 1;

    % ------ configure anti phase drive ------

    % slow
    oFRDReg.CH1_SU_SWEEP_START_FREQ1.msb = 64234;
    oFRDReg.CH1_SU_SWEEP_START_FREQ2.lsb = 233;
    oFRDReg.CH1_SU_SWEEP_STOP_FREQ1.msb = 55058;
    oFRDReg.CH1_SU_SWEEP_STOP_FREQ2.lsb = 53;
    oFRDReg.CH1_SU_SWEEP_FREQ_STEP1.msb = 2;
    oFRDReg.CH1_SU_SWEEP_FREQ_STEP2.lsb = 0;
    oFRDReg.CH1_SU.stop_condition_peak_en = 1;
    oFRDReg.CH1_SU.stop_condition_zc_en = 0;
    oFRDReg.CH1_ST_MIRRCURR_PEAK_START.cnt_value = 3822;
    oFRDReg.CH1_ST_MIRRCURR_PEAK_STOP.cnt_value = 3005;
    oFRDReg.CH1_ST_MIRRCURR_PEAK_RESET.cnt_value = 3613;
    oFRDReg.CH1_ST_MIRRCURR_PEAK_URESET.cnt_value = 3811;
    oFRDReg.CH1_ST_ADC_MIRRCURR.cnt_value = 3006;
    oFRDReg.CH1_ADC_SCHED1.angle_amplitude = 1;
    oFRDReg.CH1_SU_STOP_COND_PEAK.peak_adc_th = 2120;
    oFRDReg.CH1_SU_SWEEP.nr_of_zcs_per_f_step = 15;
    oFRDReg.CH1_SU.nr_of_good_zc_for_stop = 4;
    oFRDReg.CH1_HVD1.drive_method = 1;

    % fast
    oFRDReg.CH0_SU_SWEEP_START_FREQ1.msb = 64656;
    oFRDReg.CH0_SU_SWEEP_START_FREQ2.lsb = 260;
    oFRDReg.CH0_SU_SWEEP_STOP_FREQ1.msb = 62426;
    oFRDReg.CH0_SU_SWEEP_STOP_FREQ2.lsb = 498;
    oFRDReg.CH0_SU_SWEEP_FREQ_STEP1.msb = 0;
    oFRDReg.CH0_SU_SWEEP_FREQ_STEP2.lsb = 50;
    oFRDReg.CH0_SU.stop_condition_peak_en = 1;
    oFRDReg.CH0_SU.stop_condition_zc_en = 0;
    oFRDReg.CH0_ST_MIRRCURR_PEAK_START.cnt_value = 1174;
    oFRDReg.CH0_ST_MIRRCURR_PEAK_STOP.cnt_value = 352;
    oFRDReg.CH0_ST_MIRRCURR_PEAK_RESET.cnt_value = 964;
    oFRDReg.CH0_ST_MIRRCURR_PEAK_URESET.cnt_value = 1163;
    oFRDReg.CH0_ST_ADC_MIRRCURR.cnt_value = 353;
    oFRDReg.CH0_ADC_SCHED1.angle_amplitude = 1;
    oFRDReg.CH0_SU_STOP_COND_PEAK.peak_adc_th = 2120;
    oFRDReg.CH0_SU_SWEEP.nr_of_zcs_per_f_step = 15;
    oFRDReg.CH0_SU.nr_of_good_zc_for_stop = 4;
    oFRDReg.CH0_HVD1.drive_method = 1;

    % ------ Start slow-axis via peak-detector and wait ------
    oFRDReg.CH1_PHASE_CTRL1.bypass = 1;
    oFRDReg.CH1_CFG.CH1_CFG = 1354; % 0x054A
    oFRDReg.CH1_CFG.CH1_CFG = 1370; % 0x055A

    % wait until slow has jumped... 

    % Wait for slow axis to finish sweep
    sTimeOut = options.sTimeOut;
    sStart = tic;
    while(oFRDReg.CH1_SU.sweep_done ~= 1)
        if toc(sStart) > sTimeOut
            error('ifx:runtime_error', 'Timeout waiting for CH1_SU.sweep_done to equal 1');
        end
    end

    % ------ Start fast-axis via peak-detector and wait ------
    oFRDReg.CH0_PHASE_CTRL1.bypass = 1;
    oFRDReg.CH0_CFG.CH0_CFG = 330; % 0x014A
    oFRDReg.CH0_CFG.CH0_CFG = 346; % 0x015A

    % wait until fast has jumped... 

    % Wait for fast axis to finish sweep
    sTimeOut = options.sTimeOut;
    sStart = tic;
    while(oFRDReg.CH0_SU.sweep_done ~= 1)
        if toc(sStart) > sTimeOut
            error('ifx:runtime_error', 'Timeout waiting for CH0_SU.sweep_done to equal 1');
        end
    end

    % ------ Both axes finished sweep at this point. Change peak-detector-timings

    % Change peak-detector-timings of slow-axis.
    % =slow_st_phasedet_start
    oFRDReg.CH1_ST_MIRRCURR_PEAK_START.cnt_value = 6825;
    % =slow_st_inhibit1_hv_fast_stop
    oFRDReg.CH1_ST_MIRRCURR_PEAK_STOP.cnt_value = 175;
    % =slow_st_inhibit1_hv_fast_stop + 1
    oFRDReg.CH1_ST_ADC_MIRRCURR.cnt_value = 176;
    % =slow_st_phasedet_start - peak-detector-unreset-time [us]
    oFRDReg.CH1_ST_MIRRCURR_PEAK_URESET.cnt_value = 6814;
    % =slow_st_mirrcurr_peak_urset - peak-detector-reset-time [us]
    oFRDReg.CH1_ST_MIRRCURR_PEAK_RESET.cnt_value = 6616;
    oFRDReg.CH1_MSI1.peak_det_source = 1;

    % Change peak-detector-timings of fast-axis.
    % =fast_st_drive_on + t_in_hv_off
    oFRDReg.CH0_ST_MIRRCURR_PEAK_START.cnt_value = 974;
    % =fast_st_drive_off_min + t_lead
    oFRDReg.CH0_ST_MIRRCURR_PEAK_STOP.cnt_value = 152;
    % =fast_st_mirrcurr_peak_stop_value + 1
    oFRDReg.CH0_ST_ADC_MIRRCURR.cnt_value = 153;
    % =fast_st_mirrcurr_peak_start_value - peak-detector-unreset-time [us]
    oFRDReg.CH0_ST_MIRRCURR_PEAK_URESET.cnt_value = 963;
    % =fast_st_mirrcurr_peak_ureset_value - peak-detector-reset-time [us]
    oFRDReg.CH0_ST_MIRRCURR_PEAK_RESET.cnt_value = 764;
    oFRDReg.CH0_MSI1.peak_det_source = 1;

    % ------ Now switch to parametric-drive (if not done befeore), then set first fast-aixs to Amp-Ctrl-mode, then slow.
    oFRDReg.CH0_ST_INHIBIT1_HV_CH1_START.en = 0;
    oFRDReg.CH0_ST_INHIBIT2_HV_CH1_START.en = 0;
    % switch to parametric drive
    oFRDReg.CH0_HVD1.drive_method = 0;
    oFRDReg.CH0_PHASE_CTRL1.bypass = 0;
    oFRDReg.CH0_CFG.startup_en = 0;
    % enable amplitude control of the fast axis
    oFRDReg.CH0_CFG.ampl_ctrl_en = 1;
    oFRDReg.CH0_CFG.sfr_drive_off_en = 0;
    oFRDReg.CH1_ST_INHIBIT1_HV_CH0_START.en = 1;
    oFRDReg.CH1_ST_INHIBIT2_HV_CH0_START.en = 1;
    % switch to parametric drive
    oFRDReg.CH1_HVD1.drive_method = 0;
    oFRDReg.CH1_PHASE_CTRL1.bypass = 0;
    oFRDReg.CH1_CFG.startup_en = 0;
    % enable amplitude control of the slow axis
    oFRDReg.CH1_CFG.ampl_ctrl_en = 1;
    oFRDReg.CH1_CFG.sfr_drive_off_en = 0;

    % Wait until fast-axis is started (phase-error below 25)!
    sTimeOut = options.sTimeOut;
    sStart = tic;
    while(abs(oFRDReg.CH0_STATUS_PHASE_COMP_ERR.value) > 25)
        if toc(sStart) > sTimeOut
            error('ifx:runtime_error', 'Timeout waiting for CH0_STATUS_PHASE_COMP_ERR compensated phase error to be below 25');
        end
    end
    oFRDReg.OPR_OK2.ch0_phase_ctrl_en = 0;

    % -------- Reduce TIA gains to avoid signal overdrive
    oFRDReg.CH1_MSI1.tia_cap_sel = 5;
    oFRDReg.CH1_MSI1.tia_res_sel = 5;
    oFRDReg.CH0_MSI1.tia_cap_sel = 5;
    oFRDReg.CH0_MSI1.tia_res_sel = 5;
    % fast (master) axis is started, from now on it possible to lock to it
    oFRDReg.LJ_LOCK1.en = 1;

    % ------ Enable frequ.-control ------
    % from here FREF has to be set correctly!!
    oFRDReg.CH1_CFG.freq_ctrl_en = 1;

    % ------ Steer towards the final frequency via frequency control ------

    % Wait to reach final frequency...
    sTimeOut = options.sTimeOut;
    sStart = tic;
    while(oFRDReg.CH1_FREQ_CTRL1.f_limit_reached ~= 1)
        if toc(sStart) > sTimeOut
            error('ifx:runtime_error', 'Timeout waiting for CH1_FREQ_CTRL1.f_limit_reached to equal 1');
        end
    end

    % ------ Restart fref with smart start ------
    oFRDReg.FREF1.en = 0;
    oFRDReg.FREF_SMART_START.en = 1;
    oFRDReg.FREF1.en = 1;

    % Wait for smart-start to start up...
    sTimeOut = options.sTimeOut;
    sStart = tic;
    while(oFRDReg.FREF_SMART_START.started ~= 1)
        if toc(sStart) > sTimeOut
            error('ifx:runtime_error', 'Timeout waiting for FREF_SMART_START.started to equal 1');
        end
    end

    % ------ Do phase&frequency control for lj synch, then wait for LJ-lock ------
    oFRDReg.CH1_PHASE_CTRL1.i_gain = 118;
    oFRDReg.CH1_PHASE_CTRL2.p_gain = 395;
    oFRDReg.CH1_FREQ_CTRL1.i_gain = 3;
    oFRDReg.CH1_FREQ_CTRL2.p_gain = 2;
    oFRDReg.CH1_FREQ_CTRL3.d_gain = 8;
    oFRDReg.CH1_FREQ_CTRL3.alpha_pf = 13;
    oFRDReg.CH1_FREQ_CTRL4.d_limit_pf = 3000;
    oFRDReg.CH1_FREQ_CTRL1.source_pid = 0;

    % Wait for LJ-lock...
    sTimeOut = options.sTimeOut;
    sStart = tic;
    while(oFRDReg.LJ_LOCK1.lock ~= 1)
        if toc(sStart) > sTimeOut
            error('ifx:runtime_error', 'Timeout waiting for LJ_LOCK1.lock to equal 1');
        end
    end

    % ------ Set gains for low jitter ------
    oFRDReg.CH1_FREQ_CTRL3.d_gain = 1;
    oFRDReg.CH1_FREQ_CTRL3.alpha_pf = 5;
    oFRDReg.CH0_PHASE_CTRL1.i_gain = 6;
    oFRDReg.CH0_PHASE_CTRL2.p_gain = 60;
    oFRDReg.CH0_AMPL_CTRL1.i_gain = 1;
    oFRDReg.CH0_AMPL_CTRL2.p_gain = 20;

end